A14IEXX Positivo Unique | Physical Layer Protocols | Digital Electronics

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  5544332211D DC CB B A A TitleSize Document Number RevDate: Sheet    of  A1 26Tuesday, April 20, 2010 INDEX 5025TitleSize Document Number RevDate: Sheet    of  A1 26Tuesday, April 20, 2010 INDEX 5025TitleSize Document Number RevDate: Sheet    of  A1 26Tuesday, April 20, 2010 INDEX 5025 PCB P/NPCB DescriptionRelease DateVersionPCBA P/NNote Daughter Board Schematic Version Change List Project Name :A14IEXX PINEVIEW 2/2+1.8VS/+5VA (OZ815)9. PAGE 13.PINEVIEW 1/220.15.1.3.10. Appendix Ver.B History24.EC IT8500E / BIOSUSB /CCD/ SATA/3G21.TPT - PCI&USB&HOST 1/3TPT - Audio&SPI&GPIO 2/3 CONTENT CLOCK GEN (ICS3651)16.8.25. Appendix Ver.C History5.23.7.19. BATT IN / CHARGER (OZ8602) GPIO & Power Consumption CODEC & AMP/INT_MIC/SPK (IDT92HD81) 14. Mini Card/TP/LED22.LAN/CARDREADER(JMC261)2. CRT/LVDS TPT - POWER 3/3 VCC SW /SMART_POWER SYSTEM BLOCK DIAGRAMINDEX 17. DDR3 SODIMM +1.5V/+1.05V /3VA/0.75VS4.12.11.6.18. Platform : PineView -D + TigerPoint + DDR3 POWER DIAGRAM & SEQUENCE Release DatePCB P/NNotePCBA P/NVersionMain M/B Schematic Version Change List PCB Description CPUTIGER-POINT Rev:A0 2NDMainSHUTTLE PWR SW/FAN/HSCRP CAP/DC INCPU CORE (OZ8291)  5544332211D DC CB B A A TitleSize Document Number RevDate: Sheet    of  A2 26Tuesday, April 20, 2010 SYSTEM BLOCK DIAGRAM 5025TitleSize Document Number RevDate: Sheet    of  A2 26Tuesday, April 20, 2010 SYSTEM BLOCK DIAGRAM 5025TitleSize Document Number RevDate: Sheet    of  A2 26Tuesday, April 20, 2010 SYSTEM BLOCK DIAGRAM 5025 SMBUSRGB ITE8500EEmbedded Controller (EC) 8 Pin M-SOP GPIO Flash Rom   SPI 18 Charger  20 T/P K/B Matrix CRYSTAL 32.768KHZ 12 Pin Internal K/B PS/2SATA04GB MAX MEMORYLPCPCIE2 7,8,9 USB2 CRT 32.768KHZ RTCRJ45 25MHZ CRYSTAL SYSTEM BLOCK DIAGRAM X4 HDD x 1 2.5 SATAI/II EMC1402 800MHZDMI THERMAL SENSOR 4 Ω  1.5W x 2 IDT92HD81 Internal SPK 48 Pin LQFP TIGHTER POINT INT Mic In x 1 Codec Headphone Out x 1 CPU 200 Pin SO-DIMM0 PINEVIEW-D DDR3 RAM BUSUSB7SMBUS 0 7 Pin Battery EMC1402 CPU Thermal SensorClock Gen SMBUS 1 14.318MHZ CRYSTAL FAN 3 Pin 17 LCD PCIE1 Mini Card x 1 AZALIZALVDS WEBCAM USB0USB3SHUTTLESO-DIMM11366 * 768 one channel ODD x 1 SATA1 JMC261LAN 10/100 Cardreader  USB PORT USB1USB6 3G/USB SIMUSB BOARD USB4 USB BOARD SIM CARD3G 5,6151614185102014512121115131313171313131618 SINGLE CORE 425DUAL CORE 525  5544332211D DC CB B A A TitleSize Document Number RevDate: Sheet    of  A3 26Tuesday, April 20, 2010 POWER DIAGRAM & SEQUENCE 5025TitleSize Document Number RevDate: Sheet    of  A3 26Tuesday, April 20, 2010 POWER DIAGRAM & SEQUENCE 5025TitleSize Document Number RevDate: Sheet    of  A3 26Tuesday, April 20, 2010 POWER DIAGRAM & SEQUENCE 5025 * VCORE_ON * +3.3VS 5ms PWROK * 110ms(min)1ms45ms +3.3VS_ON * +3VA / +5VAPWRSW EC Control Pin (I/P) +5VA 0Z815VINVIN 1ms5ms5ms 5V_ON_HV 200ms20ms70ms1ms +CPU_COREOZ8291  VID1 VID6 VID0 VIN  VID4 VID2 VID5 VID3 +1.5VS +5VS 10A TDP15W  POWER BLOCK DIAGRAM PWRBTN#PM_RSMRST# 5ms +5V+1.05V_ON+3.3V+5VS+CPU_CORE * CPURST# EC Control Pin (O/P) * +0.75VS+5V_ON * System Poewr On Sequence Adaptor or BatteryPM_SLP_S3#H_PWRGDPM_SLP_S4#+1.5V ,+5Vref ** SHUTTLEP1203BVP1203BV x2+5V+3.3VAAPL1084+3.3VS+1.05V+0.75VSFP6137CG9338P1203BVP1203BVP1203BVP1203BV+3.3VP1203BVP1203BVFP6137C+1.8V * 需要兩個訊號收到後  NB  會    WORKEC 發給  NB 當  NB ready 時  SUSB SUSC 為 HI * EC 發給  NB +1.5VS_ON+1.5VS ***  NB Control Pin (O/P) ****** +1.05V 3.3VS_ON_HV
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